On Thu, Jan 10, 2019 at 09:34:10AM -0800, John Stultz wrote: > Try to add DMA support to the uart nodes following > the assignments made in the dts from the victoria vendor kernel > here: > https://consumer.huawei.com/en/opensource/detail/?siteCode=worldwide&keywords=p10&fileType=openSourceSoftware&pageSize=10&curPage=1 > > Cc: Tanglei Han <[email protected]> > Cc: Zhuangluan Su <[email protected]> > Cc: Ryan Grachek <[email protected]> > Cc: Manivannan Sadhasivam <[email protected]> > Cc: Wei Xu <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: Mark Rutland <[email protected]> > Cc: [email protected] > Cc: [email protected] > Signed-off-by: John Stultz <[email protected]>
Acked-by: Manivannan Sadhasivam <[email protected]> Thanks, Mani > --- > v3: > * Remove dma enablment on uart0 which would use reserved channel 0 > --- > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index 20ae40d..4c8d682 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -478,6 +478,8 @@ > compatible = "arm,pl011", "arm,primecell"; > reg = <0x0 0xfdf00000 0x0 0x1000>; > interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "rx", "tx"; > + dmas = <&dma0 2 &dma0 3>; > clocks = <&crg_ctrl HI3660_CLK_GATE_UART1>, > <&crg_ctrl HI3660_CLK_GATE_UART1>; > clock-names = "uartclk", "apb_pclk"; > @@ -490,6 +492,8 @@ > compatible = "arm,pl011", "arm,primecell"; > reg = <0x0 0xfdf03000 0x0 0x1000>; > interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "rx", "tx"; > + dmas = <&dma0 4 &dma0 5>; > clocks = <&crg_ctrl HI3660_CLK_GATE_UART2>, > <&crg_ctrl HI3660_PCLK>; > clock-names = "uartclk", "apb_pclk"; > @@ -514,6 +518,8 @@ > compatible = "arm,pl011", "arm,primecell"; > reg = <0x0 0xfdf01000 0x0 0x1000>; > interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "rx", "tx"; > + dmas = <&dma0 6 &dma0 7>; > clocks = <&crg_ctrl HI3660_CLK_GATE_UART4>, > <&crg_ctrl HI3660_CLK_GATE_UART4>; > clock-names = "uartclk", "apb_pclk"; > @@ -526,6 +532,8 @@ > compatible = "arm,pl011", "arm,primecell"; > reg = <0x0 0xfdf05000 0x0 0x1000>; > interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; > + dma-names = "rx", "tx"; > + dmas = <&dma0 8 &dma0 9>; > clocks = <&crg_ctrl HI3660_CLK_GATE_UART5>, > <&crg_ctrl HI3660_CLK_GATE_UART5>; > clock-names = "uartclk", "apb_pclk"; > -- > 2.7.4 >
