On 1/25/19 10:20 AM, [email protected] wrote: > From: Justin Chen <[email protected]> > > To read a channel we require 3 cycles to send, process, and receive > the data. The transfer buffer for the third transaction is left blank. > This leaves it up to the SPI driver to decide what to do. > > In one particular case, if the tx buffer is not set the spi driver > sets it to 0xff. This puts the ADC in a alarm programming state, > therefore the following read to a channel becomes erroneous. > > Instead of leaving us to the mercy of the SPI driver, we send the > ADC cmd on the third transaction to prevent inconsistent behavior. > > Fixes: 902c4b2446d4 ("iio: adc: New driver for TI ADS7950 chips") > Signed-off-by: Justin Chen <[email protected]>
Reviewed-by: Florian Fainelli <[email protected]> Thanks! -- Florian
