On 2/1/2019 4:22 AM, Peter Zijlstra wrote:
On Thu, Jan 31, 2019 at 12:27:54PM -0800, [email protected] wrote:
diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index 374a197..229a73b 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -2578,3 +2578,34 @@ void perf_get_x86_pmu_capability(struct
x86_pmu_capability *cap)
cap->events_mask_len = x86_pmu.events_mask_len;
}
EXPORT_SYMBOL_GPL(perf_get_x86_pmu_capability);
+
+u64 perf_get_page_size(u64 virt)
+{
+ unsigned long flags;
+ unsigned int level;
+ pte_t *pte;
+
+ if (!virt)
+ return 0;
+
+ /*
+ * Interrupts are disabled, so it prevents any tear down
+ * of the page tables.
+ * See the comment near struct mmu_table_batch.
+ */
+ local_irq_save(flags);
+ if (virt >= TASK_SIZE)
+ pte = lookup_address(virt, &level);
+ else {
+ if (current->mm) {
+ pte = lookup_address_in_pgd(pgd_offset(current->mm,
virt),
+ virt, &level);
+ } else
+ level = PG_LEVEL_NUM;
+ }
+ local_irq_restore(flags);
+ if (level >= PG_LEVEL_NUM)
+ return 0;
+
+ return (u64)page_level_size(level);
+}
*sigh* there really isn't anything x86 specific there.
OK. I will split the patch and move the common code to a dedicated patch
in V5. I will try the proposed code and do some tests on X86.
>> diff --git a/kernel/events/core.c b/kernel/events/core.c
index 236bb8d..d233f45 100644
--- a/kernel/events/core.c
+++ b/kernel/events/core.c
@@ -6352,6 +6358,12 @@ static u64 perf_virt_to_phys(u64 virt)
return phys_addr;
}
+/* Return page size of given virtual address. IRQ-safe required. */
+u64 __weak perf_get_page_size(u64 virt)
+{
+ return 0;
+}
+
static struct perf_callchain_entry __empty_callchain = { .nr = 0, };
struct perf_callchain_entry *
How about something like so instead?
(completely untested, will likely make your grandma eat puppies
That's not funny!
Kan
