Hi Miquel, On mar., janv. 08 2019, Miquel Raynal <[email protected]> wrote:
> The PCIe node is wired to the second PHY of the COMPHY IP. > > Suggested-by: Grzegorz Jaszczyk <[email protected]> > Signed-off-by: Miquel Raynal <[email protected]> Applied to mvebu/dt64 Thanks, Gregory > --- > arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts > b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts > index 094994a9c68e..c5c72902c647 100644 > --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts > +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts > @@ -46,6 +46,7 @@ > /* J9 */ > &pcie0 { > status = "okay"; > + phys = <&comphy1 0>; > }; > > /* J6 */ > -- > 2.19.1 > -- Gregory Clement, Bootlin Embedded Linux and Kernel engineering http://bootlin.com
