Am Donnerstag, den 07.02.2019, 16:29 -0800 schrieb Andrey Smirnov: > Add nodes for two PCIe controllers found on i.MX8MQ. > > > Signed-off-by: Andrey Smirnov <[email protected]> > > Cc: Shawn Guo <[email protected]> > > Cc: Fabio Estevam <[email protected]> > > Cc: Chris Healy <[email protected]> > > Cc: Lucas Stach <[email protected]> > > Cc: Leonard Crestez <[email protected]> > > Cc: "A.s. Dong" <[email protected]> > > Cc: Richard Zhu <[email protected]> > Cc: [email protected] > Cc: [email protected] > Cc: [email protected]
One minor thing below, otherwise: Reviewed-by: Lucas Stach <[email protected]> > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 58 +++++++++++++++++++++++ > 1 file changed, 58 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 89babc531380..8ceab748ed04 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -6,6 +6,7 @@ > > #include <dt-bindings/clock/imx8mq-clock.h> > #include <dt-bindings/power/imx8mq-power.h> > +#include <dt-bindings/reset/imx8mq-reset.h> > #include <dt-bindings/gpio/gpio.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include "imx8mq-pinfunc.h" > @@ -539,6 +540,63 @@ > > }; > > }; > > > > + pcie0: pcie@33800000 { > > + compatible = "fsl,imx8mq-pcie"; > > + reg = <0x33800000 0x400000>, > > + <0x1ff00000 0x80000>; > > + reg-names = "dbi", "config"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + bus-range = <0x00 0xff>; > > + ranges = <0x81000000 0 0x00000000 0x1ff80000 0 > > 0x00010000 /* downstream I/O 64KB */ > > + 0x82000000 0 0x18000000 0x18000000 0 > > 0x07f00000>; /* non-prefetchable memory */ > > + num-lanes = <1>; > > + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "msi"; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 125 > > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 2 &gic GIC_SPI 124 > > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 3 &gic GIC_SPI 123 > > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 4 &gic GIC_SPI 122 > > IRQ_TYPE_LEVEL_HIGH>; > > + fsl,max-link-speed = <2>; > > + power-domains = <&pgc_pcie>; > > + resets = <&src IMX8MQ_RESET_PCIEPHY>, > > + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>, > > + <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>; > > + reset-names = "pciephy", "apps", "turnoff"; > > + status = "disabled"; > > + }; > + > + pcie1: pcie@0x33c00000 { ^ Node name should not have the hex prefix in the address. > + compatible = "fsl,imx8mq-pcie"; > > + reg = <0x33c00000 0x400000>, > > + <0x27f00000 0x80000>; > > + reg-names = "dbi", "config"; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + device_type = "pci"; > > + ranges = <0x81000000 0 0x00000000 0x27f80000 0 > > 0x00010000 /* downstream I/O 64KB */ > > + 0x82000000 0 0x20000000 0x20000000 0 > > 0x07f00000>; /* non-prefetchable memory */ > > + num-lanes = <1>; > > + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "msi"; > > + #interrupt-cells = <1>; > > + interrupt-map-mask = <0 0 0 0x7>; > > + interrupt-map = <0 0 0 1 &gic GIC_SPI 77 > > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 2 &gic GIC_SPI 76 > > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 3 &gic GIC_SPI 75 > > IRQ_TYPE_LEVEL_HIGH>, > > + <0 0 0 4 &gic GIC_SPI 74 > > IRQ_TYPE_LEVEL_HIGH>; > > + fsl,max-link-speed = <2>; > > + power-domains = <&pgc_pcie>; > > + resets = <&src IMX8MQ_RESET_PCIEPHY2>, > > + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>, > > + <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>; > > + reset-names = "pciephy", "apps", "turnoff"; > > + status = "disabled"; > > + }; > + > > > gic: interrupt-controller@38800000 { > > compatible = "arm,gic-v3"; > > > reg = <0x38800000 0x10000>, /* GIC Dist */
