On 26/02/2019 07:59, Bjorn Andersson wrote:
> +static const unsigned int sdm845_pciephy_regs_layout[] = {
> + [QPHY_START_CTRL] = 0x08,
> + [QPHY_PCS_READY_STATUS] = 0x174,
> +};
> +
Just use pciephy_regs_layout?
> +static const struct qmp_phy_cfg sdm845_pciephy_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 1,
> +
> + .serdes_tbl = sdm845_pcie_serdes_tbl,
> + .serdes_tbl_num = ARRAY_SIZE(sdm845_pcie_serdes_tbl),
> + .tx_tbl = sdm845_pcie_tx_tbl,
> + .tx_tbl_num = ARRAY_SIZE(sdm845_pcie_tx_tbl),
> + .rx_tbl = sdm845_pcie_rx_tbl,
> + .rx_tbl_num = ARRAY_SIZE(sdm845_pcie_rx_tbl),
> + .pcs_tbl = sdm845_pcie_pcs_tbl,
> + .pcs_tbl_num = ARRAY_SIZE(sdm845_pcie_pcs_tbl),
> + .pcs_misc_tbl = sdm845_pcie_pcs_misc_tbl,
> + .pcs_misc_tbl_num = ARRAY_SIZE(sdm845_pcie_pcs_misc_tbl),
> + .clk_list = sdm845_pciephy_clk_l,
> + .num_clks = ARRAY_SIZE(sdm845_pciephy_clk_l),
> + .reset_list = sdm845_pciephy_reset_l,
> + .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l),
> + .vreg_list = qmp_phy_vreg_l,
> + .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
> + .regs = sdm845_pciephy_regs_layout,
pciephy_regs_layout
> +
> + .start_ctrl = PCS_START | SERDES_START,
> + .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,
> + .mask_com_pcs_ready = PCS_READY,
> +
> + .has_phy_com_ctrl = false,
> + .has_lane_rst = false,
Obviously, false entries may be omitted.
> + .has_pwrdn_delay = true,
> + .pwrdn_delay_min = 995, /* us */
> + .pwrdn_delay_max = 1005, /* us */
I think you can drop this.
Regards.
