This patch adds define for CBC field mask of the register CQHCI_SSC1. Tested-by: Jon Hunter <jonath...@nvidia.com> Acked-by: Adrian Hunter <adrian.hun...@intel.com> Signed-off-by: Sowjanya Komatineni <skomatin...@nvidia.com> --- drivers/mmc/host/cqhci.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h index 981158da3326..9fb2bb638884 100644 --- a/drivers/mmc/host/cqhci.h +++ b/drivers/mmc/host/cqhci.h @@ -88,6 +88,7 @@ /* send status config 1 */ #define CQHCI_SSC1 0x40 +#define CQHCI_SSC1_CBC_MASK GENMASK(19, 16) /* send status config 2 */ #define CQHCI_SSC2 0x44 -- 2.7.4
