3.16.65-rc1 review patch. If anyone has any objections, please let me know.
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From: Jiong Wang <jiong.w...@netronome.com>
commit 17f6c83fb5ebf7db4fcc94a5be4c22d5a7bfe428 upstream.
For micro-mips, srlv inside POOL32A encoding space should use 0x50
sub-opcode, NOT 0x90.
Some early version ISA doc describes the encoding as 0x90 for both srlv and
srav, this looks to me was a typo. I checked Binutils libopcode
implementation which is using 0x50 for srlv and 0x90 for srav.
v1->v2:
- Keep mm_srlv32_op sorted by value.
Fixes: f31318fdf324 ("MIPS: uasm: Add srlv uasm instruction")
Cc: Markos Chandras <markos.chand...@imgtec.com>
Cc: Paul Burton <paul.bur...@mips.com>
Cc: linux-m...@vger.kernel.org
Acked-by: Jakub Kicinski <jakub.kicin...@netronome.com>
Acked-by: Song Liu <songliubrav...@fb.com>
Signed-off-by: Jiong Wang <jiong.w...@netronome.com>
Signed-off-by: Alexei Starovoitov <a...@kernel.org>
Signed-off-by: Ben Hutchings <b...@decadent.org.uk>
---
arch/mips/include/uapi/asm/inst.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -262,8 +262,8 @@ enum mm_32a_minor_op {
mm_ext_op = 0x02c,
mm_pool32axf_op = 0x03c,
mm_srl32_op = 0x040,
+ mm_srlv32_op = 0x050,
mm_sra_op = 0x080,
- mm_srlv32_op = 0x090,
mm_rotr_op = 0x0c0,
mm_lwxs_op = 0x118,
mm_addu32_op = 0x150,
