On Fri, Apr 05, 2019 at 06:15:12AM -1000, Linus Torvalds wrote:
> On Fri, Apr 5, 2019 at 6:09 AM Will Deacon <[email protected]> wrote:
> > >
> > > Or did I miss something? I think the ia64() mb/rmb/wmb stuff only
> > > works on normal memory on ia64.
> >
> > I was worried about RISC-V, but actually their wmb() is "fence ow,ow"
> > which I think is stronger than their mmiowb() "fence o,w" implementation.
>
> Also with smp_store_release -> smp_load_acquire kind of ordering?
Hmm, to be honest, I'm not convinced that smp_load_acquire() is ordered
wrt subsequent I/O on RISC-V anyway, so in the pattern of:
CPU 0:
writel(1, dev);
wmb();
smp_store_release(&x, 1);
CPU 1:
if (smp_load_acquire(&x) == 1)
writel(2, dev)
then I think it's actually the control dependency in CPU 1 that provides
the expected ordering. That's probably quite fragile.
> Again, this is not at all a NAK - I think we should do this - just
> perhaps a request to add a note to the commit and make people aware of
> the issue.
Right, I'll do that.
Will
