----- On Apr 24, 2019, at 6:06 PM, Paul Burton [email protected] wrote: > Hi Mathieu, > > On Wed, Apr 24, 2019 at 11:25:02AM -0400, Mathieu Desnoyers wrote: >> diff --git a/tools/testing/selftests/rseq/rseq-mips.h >> b/tools/testing/selftests/rseq/rseq-mips.h >> index fe3eabcdcbe5..eb53a6adfbbb 100644 >> --- a/tools/testing/selftests/rseq/rseq-mips.h >> +++ b/tools/testing/selftests/rseq/rseq-mips.h >> @@ -7,7 +7,11 @@ >> * (C) Copyright 2016-2018 - Mathieu Desnoyers >> <[email protected]> >> */ >> >> -#define RSEQ_SIG 0x53053053 >> +/* >> + * RSEQ_SIG uses the break instruction. The instruction pattern is >> + * 0350000d break 0x350 >> + */ >> +#define RSEQ_SIG 0x0350000d > > My apologies for taking a while to get back to you on the various ISAs & > endian issues here, but I think we'll want this to be something like: > > #if defined(__nanomips__) > # ifdef __MIPSEL__ > # define RSEQ_SIG 0x03500010 > # else > # define RSEQ_SIG 0x00100350 > # endif > #elif defined(__mips_micromips) > # ifdef __MIPSEL__ > # define RSEQ_SIG 0xd4070000 > # else > # define RSEQ_SIG 0x0000d407 > # endif > #else > # define RSEQ_SIG 0x0350000d > #endif > > For plain old MIPS the .word directive will be fine endian-wise, but for > microMIPS & nanoMIPS we need to take into account that the instruction > stream is encoded as 16b halfwords & swap those accordingly for little > endian.
Hi Paul, Thanks for looking into it! Does the following comment above the forest of #ifdef work for you ? /* * RSEQ_SIG uses the break instruction. The instruction pattern is: * * On MIPS: * 0350000d break 0x350 * * On nanoMIPS32: * 00100350 break 0x350 * * On microMIPS: * 0000d407 break 0x350 * * For nanoMIPS32 and microMIPS, the instruction stream is encoded as 16-bit * halfwords, so the signature halfwords need to be swapped accordingly for * little-endian. */ Thanks, Mathieu -- Mathieu Desnoyers EfficiOS Inc. http://www.efficios.com
