Hi Greg,
> -----Original Message----- > From: Greg KH [mailto:[email protected]] > Sent: Thursday 25 April 2019 21:24 > To: Dragan Cvetic <[email protected]> > Cc: [email protected]; Michal Simek <[email protected]>; > [email protected]; [email protected]; Derek > Kiernan <[email protected]> > Subject: Re: [PATCH V2 01/12] dt-bindings: xilinx-sdfec: Add SDFEC binding > > On Tue, Apr 09, 2019 at 11:06:43AM +0100, Dragan Cvetic wrote: > > Add the Soft Decision Forward Error Correction (SDFEC) Engine > > bindings which is available for the Zynq UltraScale+ RFSoC > > FPGA's. > > > > Signed-off-by: Dragan Cvetic <[email protected]> > > Signed-off-by: Derek Kiernan <[email protected]> > > --- > > .../devicetree/bindings/misc/xlnx,sd-fec.txt | 58 > > ++++++++++++++++++++++ > > 1 file changed, 58 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/misc/xlnx,sd-fec.txt > > Don't you have to send new bindings to the DT maintainers? They will be in the email list from now on. Thanks Dragan > > thanks, > > greg k-h
