On Wed, Apr 10, 2019 at 01:41:39PM -0400, Yangtao Li wrote: > Allwinner Process Voltage Scaling Tables defines the voltage and > frequency value based on the speedbin blown in the efuse combination. > The sunxi-cpufreq-nvmem driver reads the efuse value from the SoC to > provide the OPP framework with required information. > This is used to determine the voltage and frequency value for each > OPP of operating-points-v2 table when it is parsed by the OPP framework. > > The "allwinner,cpu-operating-points-v2" DT extends the "operating-points-v2" > with following parameters: > - nvmem-cells (NVMEM area containig the speedbin information) > - opp-microvolt-<name>: voltage in micro Volts. > At runtime, the platform can pick a <name> and matching > opp-microvolt-<name> property. > HW: <name>: > sun50iw-h6 speed0 speed1 speed2
We already have at least one way to support speed bins with QC kryo binding. Why do we need a different way? > > Signed-off-by: Yangtao Li <[email protected]> > --- > .../bindings/opp/sunxi-nvmem-cpufreq.txt | 168 ++++++++++++++++++ > 1 file changed, 168 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/opp/sunxi-nvmem-cpufreq.txt
