cache_line_size is derived from CTR_EL0.CWG field and is called mostly
for I/O device drivers. For HiSilicon certain plantform, like the
Kunpeng920 server SoC, cache line sizes are different between L1/2
cache and L3 cache while L1 cache line size is 64-byte and L3 is 128-byte,
but CTR_EL0.CWG is misreporting using L1 cache line size.
We shall correct the right value which is important for I/O performance.
Let's update the cache line size if it is detected from DT or PPTT
information.
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Will Deacon <will.dea...@arm.com>
Cc: Sudeep Holla <sudeep.ho...@arm.com>
Cc: Jeremy Linton <jeremy.lin...@arm.com>
Reported-by: Zhenfa Qiu <qiuzhe...@hisilicon.com>
Suggested-by: Catalin Marinas <catalin.mari...@arm.com>
Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
---
arch/arm64/include/asm/cache.h | 6 +-----
arch/arm64/kernel/cacheinfo.c | 10 ++++++++++
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h
index 926434f413fa..758af6340314 100644
--- a/arch/arm64/include/asm/cache.h
+++ b/arch/arm64/include/asm/cache.h
@@ -91,11 +91,7 @@ static inline u32 cache_type_cwg(void)
#define __read_mostly __attribute__((__section__(".data..read_mostly")))
-static inline int cache_line_size(void)
-{
- u32 cwg = cache_type_cwg();
- return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
-}
+int cache_line_size(void);
/*
* Read the effective value of CTR_EL0.
diff --git a/arch/arm64/kernel/cacheinfo.c b/arch/arm64/kernel/cacheinfo.c
index 0bf0a835122f..6ffe908d476c 100644
--- a/arch/arm64/kernel/cacheinfo.c
+++ b/arch/arm64/kernel/cacheinfo.c
@@ -28,6 +28,16 @@
#define CLIDR_CTYPE(clidr, level) \
(((clidr) & CLIDR_CTYPE_MASK(level)) >> CLIDR_CTYPE_SHIFT(level))
+int cache_line_size(void)
+{
+ u32 cwg = cache_type_cwg();
+
+ if (coherency_max_size != 0)
+ return coherency_max_size;
+
+ return cwg ? 4 << cwg : ARCH_DMA_MINALIGN;
+}
+
static inline enum cache_type get_cache_type(int level)
{
u64 clidr;
--
2.7.4
