[GIT PULL] x86/cpu changes for v5.2

[Ingo Molnar]

Linus,

Please pull the latest x86-cpu-for-linus git tree from:

   git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86-cpu-for-linus

   # HEAD: 987ddbe4870b53623d76ac64044c55a13e368113 x86/power: Optimize C3 
entry on Centaur CPUs

Two changes: a Hygon CPU fix, and an optimization Centaur CPUs.

 Thanks,

        Ingo

------------------>
David Wang (1):
      x86/power: Optimize C3 entry on Centaur CPUs

Pu Wen (1):
      x86/CPU/hygon: Fix phys_proc_id calculation logic for multi-die processors


 arch/x86/kernel/acpi/cstate.c | 12 ++++++++++++
 arch/x86/kernel/cpu/hygon.c   |  5 +++++
 2 files changed, 17 insertions(+)

diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index 158ad1483c43..cb6e076a6d39 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -51,6 +51,18 @@ void acpi_processor_power_init_bm_check(struct 
acpi_processor_flags *flags,
        if (c->x86_vendor == X86_VENDOR_INTEL &&
            (c->x86 > 0xf || (c->x86 == 6 && c->x86_model >= 0x0f)))
                        flags->bm_control = 0;
+       /*
+        * For all recent Centaur CPUs, the ucode will make sure that each
+        * core can keep cache coherence with each other while entering C3
+        * type state. So, set bm_check to 1 to indicate that the kernel
+        * doesn't need to execute a cache flush operation (WBINVD) when
+        * entering C3 type state.
+        */
+       if (c->x86_vendor == X86_VENDOR_CENTAUR) {
+               if (c->x86 > 6 || (c->x86 == 6 && c->x86_model == 0x0f &&
+                   c->x86_stepping >= 0x0e))
+                       flags->bm_check = 1;
+       }
 }
 EXPORT_SYMBOL(acpi_processor_power_init_bm_check);
 
diff --git a/arch/x86/kernel/cpu/hygon.c b/arch/x86/kernel/cpu/hygon.c
index cf25405444ab..415621ddb8a2 100644
--- a/arch/x86/kernel/cpu/hygon.c
+++ b/arch/x86/kernel/cpu/hygon.c
@@ -19,6 +19,8 @@
 
 #include "cpu.h"
 
+#define APICID_SOCKET_ID_BIT 6
+
 /*
  * nodes_per_socket: Stores the number of nodes per socket.
  * Refer to CPUID Fn8000_001E_ECX Node Identifiers[10:8]
@@ -87,6 +89,9 @@ static void hygon_get_topology(struct cpuinfo_x86 *c)
                if (!err)
                        c->x86_coreid_bits = get_count_order(c->x86_max_cores);
 
+               /* Socket ID is ApicId[6] for these processors. */
+               c->phys_proc_id = c->apicid >> APICID_SOCKET_ID_BIT;
+
                cacheinfo_hygon_init_llc_id(c, cpu, node_id);
        } else if (cpu_has(c, X86_FEATURE_NODEID_MSR)) {
                u64 value;