From: Kan Liang <kan.li...@linux.intel.com>

Use generic macro PERF_REG_EXTENDED_MASK to replace PEBS_XMM_REGS to
avoid duplication.

Signed-off-by: Kan Liang <kan.li...@linux.intel.com>
---

New for V3

 arch/x86/events/core.c       |  4 ++--
 arch/x86/events/intel/ds.c   |  2 +-
 arch/x86/events/perf_event.h | 18 ------------------
 3 files changed, 3 insertions(+), 21 deletions(-)

diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c
index f315425..7708a6f 100644
--- a/arch/x86/events/core.c
+++ b/arch/x86/events/core.c
@@ -561,13 +561,13 @@ int x86_pmu_hw_config(struct perf_event *event)
        }
 
        /* sample_regs_user never support XMM registers */
-       if (unlikely(event->attr.sample_regs_user & PEBS_XMM_REGS))
+       if (unlikely(event->attr.sample_regs_user & PERF_REG_EXTENDED_MASK))
                return -EINVAL;
        /*
         * Besides the general purpose registers, XMM registers may
         * be collected in PEBS on some platforms, e.g. Icelake
         */
-       if (unlikely(event->attr.sample_regs_intr & PEBS_XMM_REGS)) {
+       if (unlikely(event->attr.sample_regs_intr & PERF_REG_EXTENDED_MASK)) {
                if (x86_pmu.pebs_no_xmm_regs)
                        return -EINVAL;
 
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index f860cdd..e6a0fa9 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -987,7 +987,7 @@ static u64 pebs_update_adaptive_cfg(struct perf_event 
*event)
                pebs_data_cfg |= PEBS_DATACFG_GP;
 
        if ((sample_type & PERF_SAMPLE_REGS_INTR) &&
-           (attr->sample_regs_intr & PEBS_XMM_REGS))
+           (attr->sample_regs_intr & PERF_REG_EXTENDED_MASK))
                pebs_data_cfg |= PEBS_DATACFG_XMMS;
 
        if (sample_type & PERF_SAMPLE_BRANCH_STACK) {
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a6ac2f4..d3b6e90 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -121,24 +121,6 @@ struct amd_nb {
         (1ULL << PERF_REG_X86_R14)   | \
         (1ULL << PERF_REG_X86_R15))
 
-#define PEBS_XMM_REGS                   \
-       ((1ULL << PERF_REG_X86_XMM0)  | \
-        (1ULL << PERF_REG_X86_XMM1)  | \
-        (1ULL << PERF_REG_X86_XMM2)  | \
-        (1ULL << PERF_REG_X86_XMM3)  | \
-        (1ULL << PERF_REG_X86_XMM4)  | \
-        (1ULL << PERF_REG_X86_XMM5)  | \
-        (1ULL << PERF_REG_X86_XMM6)  | \
-        (1ULL << PERF_REG_X86_XMM7)  | \
-        (1ULL << PERF_REG_X86_XMM8)  | \
-        (1ULL << PERF_REG_X86_XMM9)  | \
-        (1ULL << PERF_REG_X86_XMM10) | \
-        (1ULL << PERF_REG_X86_XMM11) | \
-        (1ULL << PERF_REG_X86_XMM12) | \
-        (1ULL << PERF_REG_X86_XMM13) | \
-        (1ULL << PERF_REG_X86_XMM14) | \
-        (1ULL << PERF_REG_X86_XMM15))
-
 /*
  * Per register state.
  */
-- 
2.7.4

Reply via email to