On 5/29/2019 3:54 AM, Peter Zijlstra wrote:
On Tue, May 28, 2019 at 02:24:38PM -0400, Liang, Kan wrote:
On 5/28/2019 9:43 AM, Peter Zijlstra wrote:
On Tue, May 21, 2019 at 02:40:50PM -0700, [email protected] wrote:
@@ -3287,6 +3304,13 @@ static int core_pmu_hw_config(struct perf_event *event)
return intel_pmu_bts_config(event);
}
+#define EVENT_CODE(e) (e->attr.config & INTEL_ARCH_EVENT_MASK)
+#define is_slots_event(e) (EVENT_CODE(e) == 0x0400)
+#define is_perf_metrics_event(e) \
+ (((EVENT_CODE(e) & 0xff) == 0xff) && \
+ (EVENT_CODE(e) >= 0x01ff) && \
+ (EVENT_CODE(e) <= 0x04ff))
+
That is horrific.. (e & INTEL_ARCH_EVENT_MASK) & 0xff is just daft,
that should be: (e & ARCH_PERFMON_EVENTSEL_EVENT).
Also, we already have fake events for event=0, see FIXED2, why are we
now using event=0xff ?
I think event=0 is for genuine fixed events. Metrics events are fake events.
I didn't find FIXED2 in the code. Could you please share more hints?
cd09c0c40a97 ("perf events: Enable raw event support for Intel
unhalted_reference_cycles event")
We used the fake event=0x00, umask=0x03 for CPU_CLK_UNHALTED.REF_TSC,
because that was not available as a generic event, *until now* it seems.
I see ICL actually has it as a generic event, which means we need to fix
up the constraint mask for that differently.
There is no change for REF_TSC on ICL.
But note that for all previous uarchs this event did not in fact exist.
It appears the TOPDOWN.SLOTS thing, which is available in in FIXED3 is
event=0x00, umask=0x04, is indeed a generic event too.
The SLOTS do have a generic event, TOPDOWN.SLOTS_P, event=0xA4, umask=0x1.
I think we need a fix as below for ICL, so the SLOT event can be
extended to generic event.
- FIXED_EVENT_CONSTRAINT(0x0400, 3), /* SLOTS */
+ FIXED_EVENT_CONSTRAINT(0x01a4, 3), /* TOPDOWN.SLOTS */
I will send a separate patch for it.
Thanks,
Kan
