On Tue, May 28, 2019 at 10:16:53AM +0800, Shaokun Zhang wrote: > Add coherency_max_size variable to record the maximum cache line size > for different cache levels. If it is available, we will synchronize > it as cache line size, otherwise we will use CTR_EL0.CWG reporting > in cache_line_size() for arm64. > > Cc: Greg Kroah-Hartman <gre...@linuxfoundation.org> > Cc: "Rafael J. Wysocki" <raf...@kernel.org> > Cc: Sudeep Holla <sudeep.ho...@arm.com> > Cc: Catalin Marinas <catalin.mari...@arm.com> > Cc: Jeremy Linton <jeremy.lin...@arm.com> > Cc: Will Deacon <will.dea...@arm.com> > Signed-off-by: Shaokun Zhang <zhangshao...@hisilicon.com>
Reviewed-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
