On Wed, 5 Jun 2019 at 18:54, Lukasz Luba <[email protected]> wrote: > > Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory > Controller frequencies for driver's DRAM timings. > > Acked-by: Chanwoo Choi <[email protected]> > Signed-off-by: Lukasz Luba <[email protected]> > --- > drivers/clk/samsung/clk-exynos5420.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-)
Acked-by: Krzysztof Kozlowski <[email protected]> Best regards, Krzysztof
