From: Andrey Pronin <[email protected]> Add TPM2.0 PTP FIFO compatible SPI interface for chips with Cr50 firmware.
Signed-off-by: Andrey Pronin <[email protected]> Cc: Rob Herring <[email protected]> Signed-off-by: Stephen Boyd <[email protected]> --- This is a resend of https://lkml.kernel.org/r/[email protected] with status removed. .../bindings/security/tpm/cr50_spi.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) create mode 100644 Documentation/devicetree/bindings/security/tpm/cr50_spi.txt diff --git a/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt new file mode 100644 index 000000000000..401f4ba281b7 --- /dev/null +++ b/Documentation/devicetree/bindings/security/tpm/cr50_spi.txt @@ -0,0 +1,19 @@ +* H1 Secure Microcontroller with Cr50 Firmware on SPI Bus. + +H1 Secure Microcontroller running Cr50 firmware provides several +functions, including TPM-like functionality. It communicates over +SPI using the FIFO protocol described in the PTP Spec, section 6. + +Required properties: +- compatible: Should be "google,cr50". +- spi-max-frequency: Maximum SPI frequency. + +Example: + +&spi0 { + cr50@0 { + compatible = "google,cr50"; + reg = <0>; + spi-max-frequency = <800000>; + }; +}; -- Sent by a computer through tubes
