[PATCH net-next 1/6] ocelot: Filter out ocelot SoC specific PCS config from common path

[Claudiu Manoil]

The adjust_link routine should be generic enough to be (re)used by
any SoC that integrates a switch core compatible with the Ocelot
core switch driver.  Currently all configurations are generic except
for the PCS settings that are SoC specific.  Move these out to the
Ocelot SoC/board instance.

Signed-off-by: Claudiu Manoil <claudiu.man...@nxp.com>
---
 drivers/net/ethernet/mscc/ocelot.c      | 17 ++---------------
 drivers/net/ethernet/mscc/ocelot.h      |  2 ++
 drivers/net/ethernet/mscc/ocelot_regs.c | 21 +++++++++++++++++++++
 3 files changed, 25 insertions(+), 15 deletions(-)

diff --git a/drivers/net/ethernet/mscc/ocelot.c 
b/drivers/net/ethernet/mscc/ocelot.c
index b71e4ecbe469..66cf57e6fd76 100644
--- a/drivers/net/ethernet/mscc/ocelot.c
+++ b/drivers/net/ethernet/mscc/ocelot.c
@@ -405,21 +405,8 @@ static void ocelot_port_adjust_link(struct net_device *dev)
        ocelot_port_writel(port, DEV_MAC_HDX_CFG_LATE_COL_POS(67),
                           DEV_MAC_HDX_CFG);
 
-       /* Disable HDX fast control */
-       ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
-
-       /* SGMII only for now */
-       ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA, PCS1G_MODE_CFG);
-       ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
-
-       /* Enable PCS */
-       ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
-
-       /* No aneg on SGMII */
-       ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
-
-       /* No loopback */
-       ocelot_port_writel(port, 0, PCS1G_LB_CFG);
+       if (ocelot->port_pcs_init)
+               ocelot->port_pcs_init(port);
 
        /* Set Max Length and maximum tags allowed */
        ocelot_port_writel(port, VLAN_ETH_FRAME_LEN, DEV_MAC_MAXLEN_CFG);
diff --git a/drivers/net/ethernet/mscc/ocelot.h 
b/drivers/net/ethernet/mscc/ocelot.h
index f7eeb4806897..e21a6fb22ef8 100644
--- a/drivers/net/ethernet/mscc/ocelot.h
+++ b/drivers/net/ethernet/mscc/ocelot.h
@@ -442,6 +442,8 @@ struct ocelot {
        u64 *stats;
        struct delayed_work stats_work;
        struct workqueue_struct *stats_queue;
+
+       void (*port_pcs_init)(struct ocelot_port *port);
 };
 
 struct ocelot_port {
diff --git a/drivers/net/ethernet/mscc/ocelot_regs.c 
b/drivers/net/ethernet/mscc/ocelot_regs.c
index 6c387f994ec5..000c43984858 100644
--- a/drivers/net/ethernet/mscc/ocelot_regs.c
+++ b/drivers/net/ethernet/mscc/ocelot_regs.c
@@ -412,6 +412,26 @@ static void ocelot_pll5_init(struct ocelot *ocelot)
                     HSIO_PLL5G_CFG2_AMPC_SEL(0x10));
 }
 
+static void ocelot_port_pcs_init(struct ocelot_port *port)
+{
+       /* Disable HDX fast control */
+       ocelot_port_writel(port, DEV_PORT_MISC_HDX_FAST_DIS, DEV_PORT_MISC);
+
+       /* SGMII only for now */
+       ocelot_port_writel(port, PCS1G_MODE_CFG_SGMII_MODE_ENA,
+                          PCS1G_MODE_CFG);
+       ocelot_port_writel(port, PCS1G_SD_CFG_SD_SEL, PCS1G_SD_CFG);
+
+       /* Enable PCS */
+       ocelot_port_writel(port, PCS1G_CFG_PCS_ENA, PCS1G_CFG);
+
+       /* No aneg on SGMII */
+       ocelot_port_writel(port, 0, PCS1G_ANEG_CFG);
+
+       /* No loopback */
+       ocelot_port_writel(port, 0, PCS1G_LB_CFG);
+}
+
 int ocelot_chip_init(struct ocelot *ocelot)
 {
        int ret;
@@ -420,6 +440,7 @@ int ocelot_chip_init(struct ocelot *ocelot)
        ocelot->stats_layout = ocelot_stats_layout;
        ocelot->num_stats = ARRAY_SIZE(ocelot_stats_layout);
        ocelot->shared_queue_sz = 224 * 1024;
+       ocelot->port_pcs_init = ocelot_port_pcs_init;
 
        ret = ocelot_regfields_init(ocelot, ocelot_regfields);
        if (ret)
-- 
2.17.1