On Tue, Jun 25, 2019 at 08:49:33AM +0000, Parshuram Raju Thombare wrote:
> >> switch (state->interface) {
> >> case PHY_INTERFACE_MODE_NA:
> >> + case PHY_INTERFACE_MODE_USXGMII:
> >> + case PHY_INTERFACE_MODE_10GKR:
> >> + if (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE) {
> >> + phylink_set(mask, 10000baseCR_Full);
> >> + phylink_set(mask, 10000baseER_Full);
> >> + phylink_set(mask, 10000baseKR_Full);
> >> + phylink_set(mask, 10000baseLR_Full);
> >> + phylink_set(mask, 10000baseLRM_Full);
> >> + phylink_set(mask, 10000baseSR_Full);
> >> + phylink_set(mask, 10000baseT_Full);
> >> + phylink_set(mask, 5000baseT_Full);
> >> + phylink_set(mask, 2500baseX_Full);
> >> + phylink_set(mask, 1000baseX_Full);
> >> + }
> >If MACB_CAPS_GIGABIT_MODE_AVAILABLE is not set, are these interface
> >modes supported by the hardware? If the PHY interface mode is not
> >supported, then the returned support mask must be cleared.[]
> There are some configs which uses this macro to limit data rate to 100M
> even if hardware support higher rates.
I'm sorry, this response does not address my statement, maybe I wasn't
clear enough. I am asking about the *PHY* interface modes, in
other words (e.g.) PHY_INTERFACE_MODE_USXGMII.
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