From: Will Deacon <will.dea...@arm.com>
[ Upstream commit 01d57485fcdb9f9101a10a18e32d5f8b023cab86 ]
Since commit 3d65b6bbc01e ("arm64: tlbi: Set MAX_TLBI_OPS to
PTRS_PER_PTE"), we resort to per-ASID invalidation when attempting to
perform more than PTRS_PER_PTE invalidation instructions in a single
call to __flush_tlb_range(). Whilst this is beneficial, the mmu_gather
code does not ensure that the end address of the range is rounded-up
to the stride when freeing intermediate page tables in pXX_free_tlb(),
which defeats our range checking.
Align the bounds passed into __flush_tlb_range().
Cc: Catalin Marinas <catalin.mari...@arm.com>
Cc: Peter Zijlstra <pet...@infradead.org>
Reported-by: Hanjun Guo <guohan...@huawei.com>
Tested-by: Hanjun Guo <guohan...@huawei.com>
Reviewed-by: Hanjun Guo <guohan...@huawei.com>
Signed-off-by: Will Deacon <will.dea...@arm.com>
Signed-off-by: Sasha Levin <sas...@kernel.org>
---
arch/arm64/include/asm/tlbflush.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/include/asm/tlbflush.h
b/arch/arm64/include/asm/tlbflush.h
index 3a1870228946..dff8f9ea5754 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -195,6 +195,9 @@ static inline void __flush_tlb_range(struct vm_area_struct
*vma,
unsigned long asid = ASID(vma->vm_mm);
unsigned long addr;
+ start = round_down(start, stride);
+ end = round_up(end, stride);
+
if ((end - start) >= (MAX_TLBI_OPS * stride)) {
flush_tlb_mm(vma->vm_mm);
return;
--
2.20.1
