On Thu, Jul 4, 2019 at 6:23 AM Martin Blumenstingl <[email protected]> wrote: > > Add the bindings for the PCIe PHY on Lantiq VRX200 and ARX300 SoCs. > The IP block contains settings for the PHY and a PLL. > The PLL mode is configurable through a dedicated #phy-cell in .dts. > > Signed-off-by: Martin Blumenstingl <[email protected]> > --- > .../bindings/phy/lantiq,vrx200-pcie-phy.yaml | 95 +++++++++++++++++++ > .../dt-bindings/phy/phy-lantiq-vrx200-pcie.h | 11 +++ > 2 files changed, 106 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/phy/lantiq,vrx200-pcie-phy.yaml > create mode 100644 include/dt-bindings/phy/phy-lantiq-vrx200-pcie.h
Reviewed-by: Rob Herring <[email protected]>
