Hello! On 07/25/2019 02:19 PM, Claudiu Manoil wrote:
> The on-chip PCIe root complex that integrates the ENETC ethernet > controllers also integrates a PCIe enpoint for the MDIO controller > provinding for cetralized control of the ENETC mdio bus. Providing, centralized. > Add bindings for this "central" MDIO Integrated PCIe Endpoit. > > Signed-off-by: Claudiu Manoil <[email protected]> > --- > v1 - none > v2 - none > > .../devicetree/bindings/net/fsl-enetc.txt | 42 +++++++++++++++++-- > 1 file changed, 39 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/net/fsl-enetc.txt > b/Documentation/devicetree/bindings/net/fsl-enetc.txt > index 25fc687419db..c090f6df7a39 100644 > --- a/Documentation/devicetree/bindings/net/fsl-enetc.txt > +++ b/Documentation/devicetree/bindings/net/fsl-enetc.txt [...] > @@ -47,8 +49,42 @@ Example: > }; > }; > > -2) The ENETC port is an internal port or has a fixed-link external > -connection: > +1.2. Using the central MDIO PCIe enpoint device Endpoint. -ETOOMANYTYPOS. :-) [...] MBR, Sergei
