On Mon, Jul 29, 2019 at 01:03:47PM +0300, Claudiu Manoil wrote: > LS1028a has one Ethernet management interface. On the QDS board, the > MDIO signals are multiplexed to either on-board AR8035 PHY device or > to 4 PCIe slots allowing for SGMII cards. > To enable the Ethernet ENETC Port 1, which can only be connected to a > RGMII PHY, the multiplexer needs to be configured to route the MDIO to > the AR8035 PHY. The MDIO/MDC routing is controlled by bits 7:4 of FPGA > board config register 0x54, and value 0 selects the on-board RGMII PHY. > The FPGA board config registers are accessible on the i2c bus, at address > 0x66. > > The PF3 MDIO PCIe integrated endpoint device allows for centralized access > to the MDIO bus. Add the corresponding devicetree node and set it to be > the MDIO bus parent. > > Signed-off-by: Alex Marginean <[email protected]> > Signed-off-by: Claudiu Manoil <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]> Andrew
