The high frequency pll functionality is required to enable CPU
frequency scaling operation.

Co-developed-by: Niklas Cassel <niklas.cas...@linaro.org>
Signed-off-by: Niklas Cassel <niklas.cas...@linaro.org>
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-or...@linaro.org>
Reviewed-by: Bjorn Andersson <bjorn.anders...@linaro.org>
---
 arch/arm64/boot/dts/qcom/qcs404.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi 
b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index a97eeb4569c0..75ea356a3fb0 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -869,6 +869,15 @@
                        #mbox-cells = <1>;
                };
 
+               apcs_hfpll: clock-controller@b016000 {
+                       compatible = "qcom,hfpll";
+                       reg = <0x0b016000 0x30>;
+                       #clock-cells = <0>;
+                       clock-output-names = "apcs_hfpll";
+                       clocks = <&xo_board>;
+                       clock-names = "xo";
+               };
+
                timer@b120000 {
                        #address-cells = <1>;
                        #size-cells = <1>;
-- 
2.22.0

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