[PATCH net-next 11/12] net: hns3: check reset interrupt status when reset fails

[Huazhong Tan]

Currently, the reset interrupt will be cleared firstly, so when
reset fails, if interrupt status register has reset interrupt,
it means there is a new coming reset.

Fixes: 72e2fb07997c ("net: hns3: clear reset interrupt status in 
hclge_irq_handle()")
Signed-off-by: Huazhong Tan <tanhuazh...@huawei.com>
Reviewed-by: Peng Li <lipeng...@huawei.com>
---
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 7 +++----
 drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h | 1 +
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c 
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 428f7c0..dc22b84 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -3536,11 +3536,10 @@ static bool hclge_reset_err_handle(struct hclge_dev 
*hdev)
                dev_info(&hdev->pdev->dev, "Reset pending %lu\n",
                         hdev->reset_pending);
                return true;
-       } else if ((hdev->reset_type != HNAE3_IMP_RESET) &&
-                  (hclge_read_dev(&hdev->hw, HCLGE_GLOBAL_RESET_REG) &
-                   BIT(HCLGE_IMP_RESET_BIT))) {
+       } else if (hclge_read_dev(&hdev->hw, HCLGE_MISC_VECTOR_INT_STS) &
+                  HCLGE_RESET_INT_M) {
                dev_info(&hdev->pdev->dev,
-                        "reset failed because IMP Reset is pending\n");
+                        "reset failed because new reset interrupt\n");
                hclge_clear_reset_cause(hdev);
                return false;
        } else if (hdev->reset_fail_cnt < MAX_RESET_FAIL_CNT) {
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h 
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
index a3bc382..437a9ff 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
@@ -164,6 +164,7 @@ enum HLCGE_PORT_TYPE {
 #define HCLGE_GLOBAL_RESET_BIT         0
 #define HCLGE_CORE_RESET_BIT           1
 #define HCLGE_IMP_RESET_BIT            2
+#define HCLGE_RESET_INT_M              GENMASK(2, 0)
 #define HCLGE_FUN_RST_ING              0x20C00
 #define HCLGE_FUN_RST_ING_B            0
 
-- 
2.7.4