Jerome Brunet <[email protected]> writes: > The meson sm1 SoCs uses the same type of GPIO interrupt controller IP > block as the other meson SoCs, A total of 100 pins can be spied on: > > - 223:100 undefined (no interrupt) > - 99:97 3 pins on bank GPIOE > - 96:77 20 pins on bank GPIOX > - 76:61 16 pins on bank GPIOA > - 60:53 8 pins on bank GPIOC > - 52:37 16 pins on bank BOOT > - 36:28 9 pins on bank GPIOH > - 27:12 16 pins on bank GPIOZ > - 11:0 12 pins in the AO domain > > Mapping is the same as the g12a family but the sm1 controller > allows to trig an irq on both edges of the input signal. This was > not possible with the previous SoCs families > > Signed-off-by: Jerome Brunet <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]> Tested-by: Kevin Hilman <[email protected]> > --- > drivers/irqchip/irq-meson-gpio.c | 52 +++++++++++++++++++++++--------- > 1 file changed, 38 insertions(+), 14 deletions(-) > > diff --git a/drivers/irqchip/irq-meson-gpio.c > b/drivers/irqchip/irq-meson-gpio.c > index dcdc23b9dce6..829084b568fa 100644 > --- a/drivers/irqchip/irq-meson-gpio.c > +++ b/drivers/irqchip/irq-meson-gpio.c > @@ -24,14 +24,25 @@ > #define REG_PIN_47_SEL 0x08 > #define REG_FILTER_SEL 0x0c > > -#define REG_EDGE_POL_MASK(x) (BIT(x) | BIT(16 + (x))) > +/* > + * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by > + * bits 24 to 31. Tests on the actual HW show that these bits are > + * stuck at 0. Bits 8 to 15 are responsive and have the expected > + * effect. > + */ nice catch! Kevin
