[PATCH V2 08/12] serial: tegra: add support to use 8 bytes trigger

[Krishna Yarlagadda]

Add support to use 8 bytes trigger for Tegra186 SOC.

Signed-off-by: Shardar Shariff Md <smoham...@nvidia.com>
Signed-off-by: Krishna Yarlagadda <kyarlaga...@nvidia.com>
---
 drivers/tty/serial/serial-tegra.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/tty/serial/serial-tegra.c 
b/drivers/tty/serial/serial-tegra.c
index 8422516..02f8535 100644
--- a/drivers/tty/serial/serial-tegra.c
+++ b/drivers/tty/serial/serial-tegra.c
@@ -88,6 +88,7 @@ struct tegra_uart_chip_data {
        bool    support_clk_src_div;
        bool    fifo_mode_enable_status;
        int     uart_max_port;
+       int     max_dma_burst_bytes;
 };
 
 struct tegra_uart_port {
@@ -931,7 +932,12 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup)
         * programmed in the DMA registers.
         */
        tup->fcr_shadow = UART_FCR_ENABLE_FIFO;
-       tup->fcr_shadow |= UART_FCR_R_TRIG_01;
+
+       if (tup->cdata->max_dma_burst_bytes == 8)
+               tup->fcr_shadow |= UART_FCR_R_TRIG_10;
+       else
+               tup->fcr_shadow |= UART_FCR_R_TRIG_01;
+
        tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B;
        tegra_uart_write(tup, tup->fcr_shadow, UART_FCR);
 
@@ -1045,7 +1051,7 @@ static int tegra_uart_dma_channel_allocate(struct 
tegra_uart_port *tup,
                }
                dma_sconfig.src_addr = tup->uport.mapbase;
                dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
-               dma_sconfig.src_maxburst = 4;
+               dma_sconfig.src_maxburst = tup->cdata->max_dma_burst_bytes;
                tup->rx_dma_chan = dma_chan;
                tup->rx_dma_buf_virt = dma_buf;
                tup->rx_dma_buf_phys = dma_phys;
@@ -1324,6 +1330,7 @@ static struct tegra_uart_chip_data tegra20_uart_chip_data 
= {
        .support_clk_src_div            = false,
        .fifo_mode_enable_status        = false,
        .uart_max_port                  = 5,
+       .max_dma_burst_bytes            = 4,
 };
 
 static struct tegra_uart_chip_data tegra30_uart_chip_data = {
@@ -1332,6 +1339,7 @@ static struct tegra_uart_chip_data tegra30_uart_chip_data 
= {
        .support_clk_src_div            = true,
        .fifo_mode_enable_status        = false,
        .uart_max_port                  = 5,
+       .max_dma_burst_bytes            = 4,
 };
 
 static struct tegra_uart_chip_data tegra186_uart_chip_data = {
@@ -1340,6 +1348,7 @@ static struct tegra_uart_chip_data 
tegra186_uart_chip_data = {
        .support_clk_src_div            = true,
        .fifo_mode_enable_status        = true,
        .uart_max_port                  = 8,
+       .max_dma_burst_bytes            = 8,
 };
 
 static const struct of_device_id tegra_uart_of_match[] = {
-- 
2.7.4