From: Vitaly Gaiduk <[email protected]> Date: Mon, 9 Sep 2019 20:19:24 +0300
> This patch adds ability to switch beetween two PHY SGMII modes. > Some hardware, for example, FPGA IP designs may use 6-wire mode > which enables differential SGMII clock to MAC. > > Signed-off-by: Vitaly Gaiduk <[email protected]> Applied.
