On Thu, Sep 12, 2019 at 06:32:06PM -0700, Megha Dey wrote:
> This patch introduces an x86 specific indirect mechanism to setup the
> interrupt message storage. The IMS specific functions (setup, teardown,
> restore) become function pointers in an x86_ims_ops struct, that
> defaults to their implementations in ims.c and ims-msi.c.
>
> Cc: Jacob Pan <jacob.jun....@linux.intel.com>
> Signed-off-by: Sanjay Kumar <sanjay.k.ku...@intel.com>
> Signed-off-by: Megha Dey <megha....@linux.intel.com>
> arch/x86/include/asm/pci.h | 4 ++++
> arch/x86/include/asm/x86_init.h | 10 ++++++++++
> arch/x86/kernel/apic/ims.c | 18 ++++++++++++++++++
> arch/x86/kernel/x86_init.c | 23 +++++++++++++++++++++++
> drivers/base/ims-msi.c | 34 ++++++++++++++++++++++++++++++++++
> include/linux/msi.h | 6 ++++++
> 6 files changed, 95 insertions(+)
>
> diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
> index e662f98..2ef513f 100644
> +++ b/arch/x86/include/asm/pci.h
> @@ -114,6 +114,10 @@ struct msi_desc;
> int native_setup_msi_irqs(struct pci_dev *dev, int nvec, int type);
> void native_teardown_msi_irq(unsigned int irq);
> void native_restore_msi_irqs(struct pci_dev *dev);
> +#ifdef CONFIG_MSI_IMS
> +int native_setup_ims_irqs(struct device *dev, int nvec);
> +#endif
> +
> #else
> #define native_setup_msi_irqs NULL
> #define native_teardown_msi_irq NULL
> diff --git a/arch/x86/include/asm/x86_init.h b/arch/x86/include/asm/x86_init.h
> index ac09341..9c2cbbb 100644
> +++ b/arch/x86/include/asm/x86_init.h
> @@ -287,6 +287,15 @@ struct x86_msi_ops {
> void (*restore_msi_irqs)(struct pci_dev *dev);
> };
>
> +struct device;
> +
> +struct x86_ims_ops {
> + int (*setup_ims_irqs)(struct device *dev, int nvec);
> + void (*teardown_ims_irq)(unsigned int irq);
> + void (*teardown_ims_irqs)(struct device *dev);
> + void (*restore_ims_irqs)(struct device *dev);
> +};
This looks alot like the generic struct msi_controller..
Jason
