[PATCH v3 4/4] x86/mce: Add Zhaoxin LMCE support

[Tony W Wang-oc]

Zhaoxin newer CPUs support LMCE that compatible with Intel's
"Machine-Check Architecture", so add support for Zhaoxin LMCE
in mce/core.c.

Signed-off-by: Tony W Wang-oc <tonywwang...@zhaoxin.com>
---
 arch/x86/kernel/cpu/mce/core.c | 35 +++++++++++++++++++++++++++++++++--
 1 file changed, 33 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
index 65c5a1f..acdd76b 100644
--- a/arch/x86/kernel/cpu/mce/core.c
+++ b/arch/x86/kernel/cpu/mce/core.c
@@ -1132,6 +1132,27 @@ static bool __mc_check_crashing_cpu(int cpu)
                u64 mcgstatus;
 
                mcgstatus = mce_rdmsrl(MSR_IA32_MCG_STATUS);
+
+               if (boot_cpu_data.x86_vendor == X86_VENDOR_ZHAOXIN) {
+                       if (mcgstatus & MCG_STATUS_LMCES)
+                               return false;
+
+                       if (!(mcgstatus & MCG_STATUS_LMCES)) {
+                               /*
+                                * Clear the MCG_STATUS_RIPV valid status
+                                * bit so that a second MCE won't cause a
+                                * shutdown.
+                                */
+                               if (mcgstatus & MCG_STATUS_RIPV)
+                                       mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
+                               /*
+                                * On this CPU, skip synchronize regardless
+                                * of MCG_STATUS_RIPV status.
+                                */
+                               return true;
+                       }
+               }
+
                if (mcgstatus & MCG_STATUS_RIPV) {
                        mce_wrmsrl(MSR_IA32_MCG_STATUS, 0);
                        return true;
@@ -1282,9 +1303,10 @@ void do_machine_check(struct pt_regs *regs, long 
error_code)
 
        /*
         * Check if this MCE is signaled to only this logical processor,
-        * on Intel only.
+        * on Intel, Zhaoxin only.
         */
-       if (m.cpuvendor == X86_VENDOR_INTEL)
+       if (m.cpuvendor == X86_VENDOR_INTEL ||
+           m.cpuvendor == X86_VENDOR_ZHAOXIN)
                lmce = m.mcgstatus & MCG_STATUS_LMCES;
 
        /*
@@ -1795,9 +1817,15 @@ static void mce_zhaoxin_feature_init(struct cpuinfo_x86 
*c)
        }
 
        intel_init_cmci();
+       intel_init_lmce();
        mce_adjust_timer = cmci_intel_adjust_timer;
 }
 
+static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c)
+{
+       intel_clear_lmce();
+}
+
 static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c)
 {
        switch (c->x86_vendor) {
@@ -1834,6 +1862,9 @@ static void __mcheck_cpu_clear_vendor(struct cpuinfo_x86 
*c)
        case X86_VENDOR_INTEL:
                mce_intel_feature_clear(c);
                break;
+       case X86_VENDOR_ZHAOXIN:
+               mce_zhaoxin_feature_clear(c);
+               break;
        default:
                break;
        }
-- 
2.7.4