From: Rasmus Villemoes <[email protected]> This adds Device Tree binding documentation for the external interrupt lines with configurable polarity present on some Layerscape SOCs.
Signed-off-by: Rasmus Villemoes <[email protected]> Signed-off-by: Kurt Kanzenbach <[email protected]> --- Changes since v5: - Add #address-cells and #size-cells to parent - Mention LS2088A and the ISC unit .../interrupt-controller/fsl,ls-extirq.txt | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt new file mode 100644 index 000000000000..7b53f9cc8019 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-extirq.txt @@ -0,0 +1,47 @@ +* Freescale Layerscape external IRQs + +Some Layerscape SOCs (LS1021A, LS1043A, LS1046A, LS2088A) support +inverting the polarity of certain external interrupt lines. + +The device node must be a child of the node representing the +Supplemental Configuration Unit (SCFG) or the Interrupt Sampling +Control (ISC) Unit. + +Required properties: +- compatible: should be "fsl,<soc-name>-extirq", e.g. "fsl,ls1021a-extirq". +- interrupt-controller: Identifies the node as an interrupt controller +- #interrupt-cells: Must be 2. The first element is the index of the + external interrupt line. The second element is the trigger type. +- interrupt-parent: phandle of GIC. +- reg: Specifies the Interrupt Polarity Control Register (INTPCR) in the SCFG. +- fsl,extirq-map: Specifies the mapping to interrupt numbers in the parent + interrupt controller. Interrupts are mapped one-to-one to parent + interrupts. + +Optional properties: +- fsl,bit-reverse: This boolean property should be set on the LS1021A + if the SCFGREVCR register has been set to all-ones (which is usually + the case), meaning that all reads and writes of SCFG registers are + implicitly bit-reversed. Other compatible platforms do not have such + a register. + +Example: + scfg: scfg@1570000 { + compatible = "fsl,ls1021a-scfg", "syscon"; + #address-cells = <1>; + #size-cells = <0>; + ... + extirq: interrupt-controller { + compatible = "fsl,ls1021a-extirq"; + #interrupt-cells = <2>; + interrupt-controller; + interrupt-parent = <&gic>; + reg = <0x1ac>; + fsl,extirq-map = <163 164 165 167 168 169>; + fsl,bit-reverse; + }; + }; + + + interrupts-extended = <&gic GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, + <&extirq 1 IRQ_TYPE_LEVEL_LOW>; -- 2.20.1
