Add necessary compatible flag for HiSi's DWC3 so dwc3-of-simple will probe.
Cc: Greg Kroah-Hartman <[email protected]> Cc: Felipe Balbi <[email protected]> Cc: Andy Shevchenko <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Yu Chen <[email protected]> Cc: Matthias Brugger <[email protected]> Cc: Chunfeng Yun <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: John Stultz <[email protected]> --- .../devicetree/bindings/usb/hisi,dwc3.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/usb/hisi,dwc3.txt diff --git a/Documentation/devicetree/bindings/usb/hisi,dwc3.txt b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt new file mode 100644 index 000000000000..dc31b8a3c006 --- /dev/null +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt @@ -0,0 +1,52 @@ +HiSi SuperSpeed DWC3 USB SoC controller + +Required properties: +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC +- clocks: A list of phandle + clock-specifier pairs for the + clocks listed in clock-names +- clock-names: Should contain the following: + "clk_usb3phy_ref" Phy reference clk + "aclk_usb3otg" USB3 OTG aclk + +- assigned-clocks: Should be: + HI3660_ACLK_GATE_USB3OTG +- assigned-clock-rates: Should be: + 229Mhz (229000000) for HI3660_ACLK_GATE_USB3OTG + +Optional properties: +- resets: Phandle to reset control that resets core and wrapper. + +Required child node: +A child node must exist to represent the core DWC3 IP block. The name of +the node is not important. The content of the node is defined in dwc3.txt. + +Example device nodes: + + usb3: hisi_dwc3 { + compatible = "hisilicon,hi3660-dwc3"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>, + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + clock-names = "clk_usb3phy_ref", "aclk_usb3otg"; + + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>; + assigned-clock-rates = <229 000 000>; + resets = <&crg_rst 0x90 8>, + <&crg_rst 0x90 7>, + <&crg_rst 0x90 6>, + <&crg_rst 0x90 5>; + + dwc3: dwc3@ff100000 { + compatible = "snps,dwc3"; + reg = <0x0 0xff100000 0x0 0x100000>; + interrupts = <0 159 4>, <0 161 4>; + phys = <&usb_phy>; + phy-names = "usb3-phy"; + dr_mode = "otg"; + + ... + }; + }; -- 2.17.1
