On Thu, Sep 26, 2019 at 9:43 PM Gayatri Kammela <[email protected]> wrote:
Thank you for the series, I'll comment them later. For now, check how to properly setup prefix for all patches. The Title all broken. > Patch 1: Cleans up termination lines > Patch 2: Refactor driver for ease of adding new SoCs > Patch 3: Refactor debugfs entry for PCH IPs power gating status > Patch 4: Add Tiger Lake legacy support to pmc_core > Patch 5: Add Elkhart Lake legacy support to pmc_core > > All the information regarding the PCH IPs and names of IPs will be available > in *future* Intel's Platform Controller Hub (PCH) External Design > Specification > (EDS) document. When? > Gayatri Kammela (5): > x86/intel_pmc_core: Clean up: Remove comma after the termination line > x86/intel_pmc_core: Create platform dependent pmc bitmap structs > x86/intel_pmc_core: Make debugfs entry for pch_ip_power_gating_status > conditional > platform/x86: Add Tiger Lake(TGL) platform support to intel_pmc_core > driver > platform/x86: Add Atom based Elkhart Lake(EHL) platform support to > intel_pmc_core driver > > drivers/platform/x86/intel_pmc_core.c | 108 +++++++++++++++++++++----- > drivers/platform/x86/intel_pmc_core.h | 2 +- > 2 files changed, 88 insertions(+), 22 deletions(-) > > Cc: Peter Zijlstra <[email protected]> > Cc: Srinivas Pandruvada <[email protected]> > Cc: Andy Shevchenko <[email protected]> > Cc: Kan Liang <[email protected]> > Cc: David E. Box <[email protected]> > Cc: Rajneesh Bhardwaj <[email protected]> > Cc: Tony Luck <[email protected]> > Reviewed-by: Tony Luck <[email protected]> > -- > 2.17.1 > -- With Best Regards, Andy Shevchenko
