Hi,

On Tue, Oct 01, 2019 at 10:06:56PM +0200, Jernej Skrabec wrote:
> GPU PLL was designed with dynamic frequency switching in mind so driver
> can adjust rate based on the GPU load.
>
> Allow GPU clock to change parent rate (GPU PLL is the only possible
> parent of GPU clock).
>
> Signed-off-by: Jernej Skrabec <[email protected]>
> ---
>  drivers/clk/sunxi-ng/ccu-sun50i-h6.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c 
> b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> index d89353a3cdec..e254c06c8621 100644
> --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6.c
> @@ -290,7 +290,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(gpu_clk, "gpu", 
> gpu_parents, 0x670,
>                                      0, 3,    /* M */
>                                      24, 1,   /* mux */
>                                      BIT(31), /* gate */
> -                                    0);
> +                                    CLK_SET_RATE_PARENT);
>
>  static SUNXI_CCU_GATE(bus_gpu_clk, "bus-gpu", "psi-ahb1-ahb2",
>                     0x67c, BIT(0), 0);

Applied, thanks!
Maxime

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