On Fri, Sep 20, 2019 at 04:34:18PM +0800, Wen He wrote: > In order to maximise performance of the LCD Controller's 64-bit AXI > bus, for any give speed bin of the device, the AXI master interface > clock(ACLK) clock can be up to CPU_frequency/2, which is already > capable of optimal performance. In general, ACLK is always expected > to be equal to CPU_frequency/2. APB slave interface clock(PCLK) and > Main processing clock(PCLK) both are tied to the same clock as ACLK. > > This change followed the LS1028A Architecture Specification Manual. > > Signed-off-by: Wen He <[email protected]>
Applied, thanks.
