On Wed, Apr 29, 2020 at 11:37:37AM +0800, ryan_chen wrote: > In AST2600 there have a slow peripheral bus between CPU > and i2c controller. > Therefore GIC i2c interrupt status clear have delay timing, > when CPU issue write clear i2c controller interrupt status. > To avoid this issue, the driver need have read after write > clear at i2c ISR. > > Signed-off-by: ryan_chen <ryan_c...@aspeedtech.com>
Applied to for-current with a Fixes tag, thanks! Please, try to add one next time and please also check how the subsystem formats the $subject line.
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