On Fri, 2020-05-01 at 10:28 -0400, Jim Quinlan wrote: > From: Jim Quinlan <[email protected]> > > Some informal internal experiments has shown that the BrcmSTB ASPM L0s > savings may introduce an undesirable noise signal on some customers' > boards. In addition, L0s was found lacking in realized power savings, > especially relative to the L1 ASPM component. This is BrcmSTB's > experience and may not hold for others. At any rate, if the > 'aspm-no-l0s' property is present L0s will be disabled. > > Signed-off-by: Jim Quinlan <[email protected]> > Acked-by: Florian Fainelli <[email protected]>
Modulo the new generic dt property: Acked-by: Nicolas Saenz Julienne <[email protected]> Regards, Nicolas > --- > drivers/pci/controller/pcie-brcmstb.c | 14 +++++++++++++- > 1 file changed, 13 insertions(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c > b/drivers/pci/controller/pcie-brcmstb.c > index 5b0dec5971b8..73020b4ff090 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -41,6 +41,9 @@ > #define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c > #define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff > > +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc > +#define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 > + > #define PCIE_RC_DL_MDIO_ADDR 0x1100 > #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 > #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 > @@ -693,7 +696,7 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > int num_out_wins = 0; > u16 nlw, cls, lnksta; > int i, ret; > - u32 tmp; > + u32 tmp, aspm_support; > > /* Reset the bridge */ > brcm_pcie_bridge_sw_init_set(pcie, 1); > @@ -803,6 +806,15 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) > num_out_wins++; > } > > + /* Don't advertise L0s capability if 'aspm-no-l0s' */ > + aspm_support = PCIE_LINK_STATE_L1; > + if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) > + aspm_support |= PCIE_LINK_STATE_L0S; > + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); > + u32p_replace_bits(&tmp, aspm_support, > + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK); > + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); > + > /* > * For config space accesses on the RC, show the right class for > * a PCIe-PCIe bridge (the default setting is to be EP mode).
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