On Tue, May 05, 2020 at 03:15:29PM +0100, Daniel Thompson wrote: > On Mon, May 04, 2020 at 09:48:04PM +0100, Will Deacon wrote: > > On Mon, May 04, 2020 at 06:05:18PM +0100, Daniel Thompson wrote: > > > diff --git a/arch/arm64/include/asm/cacheflush.h > > > b/arch/arm64/include/asm/cacheflush.h > > > index e6cca3d4acf7..ce50c1f1f1ea 100644 > > > --- a/arch/arm64/include/asm/cacheflush.h > > > +++ b/arch/arm64/include/asm/cacheflush.h > > > @@ -79,7 +79,7 @@ static inline void flush_icache_range(unsigned long > > > start, unsigned long end) > > > * IPI all online CPUs so that they undergo a context synchronization > > > * event and are forced to refetch the new instructions. > > > */ > > > -#ifdef CONFIG_KGDB > > > + > > > /* > > > * KGDB performs cache maintenance with interrupts disabled, so we > > > * will deadlock trying to IPI the secondary CPUs. In theory, we can > > > @@ -89,9 +89,9 @@ static inline void flush_icache_range(unsigned long > > > start, unsigned long end) > > > * the patching operation, so we don't need extra IPIs here anyway. > > > * In which case, add a KGDB-specific bodge and return early. > > > */ > > > - if (kgdb_connected && irqs_disabled()) > > > + if (in_dbg_master()) > > > > Does this imply that irqs are disabled? > > Yes. > > Assuming CONFIG_KGDB is enabled then in_dbg_master() expands to: > > (raw_smp_processor_id() == atomic_read(&kgdb_active))
Aha, so this can drop the raw_ prefix and call smp_processor_id() instead? I can queue the arm64 patch regardless. Cheers, Will
