On Fri, May 08, 2020 at 01:53:04PM +0300, Serge Semin wrote: > Full multi-block transfers functionality is enabled in DW DMA > controller only if CHx_MULTI_BLK_EN is set. But LLP-based transfers > can be executed only if hardcode channel x LLP register feature isn't > enabled, which can be switched on at the IP core synthesis for > optimization. If it's enabled then the LLP register is hardcoded to > zero, so the blocks chaining based on the LLPs is unsupported. >
This one is good. Reviewed-by: Andy Shevchenko <[email protected]> Feel free to reassemble the series, so, Vinod can apply it independently. > Signed-off-by: Serge Semin <[email protected]> > Cc: Alexey Malahov <[email protected]> > Cc: Thomas Bogendoerfer <[email protected]> > Cc: Paul Burton <[email protected]> > Cc: Ralf Baechle <[email protected]> > Cc: Arnd Bergmann <[email protected]> > Cc: Andy Shevchenko <[email protected]> > Cc: Dan Williams <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: [email protected] > Cc: [email protected] > > --- > > Changelog v2: > - Rearrange SoBs. > - Add comment about why hardware accelerated LLP list support depends > on both MBLK_EN and HC_LLP configs setting. > - Use explicit bits state comparison operator. > --- > drivers/dma/dw/core.c | 11 ++++++++++- > drivers/dma/dw/regs.h | 1 + > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c > index 5b76ccc857fd..3179d45df662 100644 > --- a/drivers/dma/dw/core.c > +++ b/drivers/dma/dw/core.c > @@ -1180,8 +1180,17 @@ int do_dma_probe(struct dw_dma_chip *chip) > */ > dwc->block_size = > (4 << ((pdata->block_size >> 4 * i) & 0xf)) - 1; > + > + /* > + * According to the DW DMA databook the true scatter- > + * gether LLPs aren't available if either multi-block > + * config is disabled (CHx_MULTI_BLK_EN == 0) or the > + * LLP register is hard-coded to zeros > + * (CHx_HC_LLP == 1). > + */ > dwc->nollp = > - (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0; > + (dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0 || > + (dwc_params >> DWC_PARAMS_HC_LLP & 0x1) == 1; > dwc->max_burst = > (0x4 << (dwc_params >> DWC_PARAMS_MSIZE & 0x7)); > } else { > diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h > index f581d4809b71..a8af19d0eabd 100644 > --- a/drivers/dma/dw/regs.h > +++ b/drivers/dma/dw/regs.h > @@ -126,6 +126,7 @@ struct dw_dma_regs { > > /* Bitfields in DWC_PARAMS */ > #define DWC_PARAMS_MSIZE 16 /* max group transaction size */ > +#define DWC_PARAMS_HC_LLP 13 /* set LLP register to zero */ > #define DWC_PARAMS_MBLK_EN 11 /* multi block transfer */ > > /* bursts size */ > -- > 2.25.1 > -- With Best Regards, Andy Shevchenko
