This adds reset support to the Sparx5 SoC
Signed-off-by: Lars Povlsen <[email protected]>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi
b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index b5cb3d8dc876b..3e94ac9e7dd51 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -106,6 +106,17 @@ gic: interrupt-controller@600300000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ cpu_ctrl: syscon@600000000 {
+ compatible = "microchip,sparx5-cpu-syscon", "syscon";
+ reg = <0x6 0x00000000 0xd0>;
+ };
+
+ reset@611010008 {
+ compatible = "microchip,sparx5-chip-reset";
+ reg = <0x6 0x11010008 0x4>;
+ microchip,reset-switch-core;
+ };
+
uart0: serial@600100000 {
pinctrl-0 = <&uart_pins>;
pinctrl-names = "default";
--
2.26.2
