This adds SGPIO devices for the Sparx5 SoC and configures it for the applicable reference boards.
Reviewed-by: Alexandre Belloni <[email protected]> Signed-off-by: Lars Povlsen <[email protected]> --- arch/arm64/boot/dts/microchip/sparx5.dtsi | 52 +++++++++++++++++++ .../boot/dts/microchip/sparx5_pcb125.dts | 5 ++ .../dts/microchip/sparx5_pcb134_board.dtsi | 5 ++ 3 files changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi index 60629861a5157..b4fda5616536c 100644 --- a/arch/arm64/boot/dts/microchip/sparx5.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi @@ -213,6 +213,22 @@ si2_pins: si2-pins { function = "si2"; }; + sgpio0_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + sgpio1_pins: sgpio1-pins { + pins = "GPIO_4", "GPIO_5", "GPIO_12", "GPIO_13"; + function = "sg1"; + }; + + sgpio2_pins: sgpio2-pins { + pins = "GPIO_30", "GPIO_31", "GPIO_32", + "GPIO_33"; + function = "sg2"; + }; + uart_pins: uart-pins { pins = "GPIO_10", "GPIO_11"; function = "uart"; @@ -243,6 +259,42 @@ emmc_pins: emmc-pins { }; }; + sgpio0: gpio@61101036c { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio0_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101036c 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 64 64>; + }; + + sgpio1: gpio@611010484 { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio1_pins>; + pinctrl-names = "default"; + reg = <0x6 0x11010484 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 128 64>; + }; + + sgpio2: gpio@61101059c { + compatible = "mscc,ocelot-sgpio"; + status = "disabled"; + clocks = <&sys_clk>; + pinctrl-0 = <&sgpio2_pins>; + pinctrl-names = "default"; + reg = <0x6 0x1101059c 0x100>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 192 64>; + }; + i2c0: i2c@600101000 { compatible = "snps,designware-i2c"; status = "disabled"; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts index 94c4c3fd5a786..fd4f5b3ddcc49 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts @@ -55,6 +55,11 @@ spi-flash@1 { }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-ports = <0x00FFFFFF>; +}; + &i2c1 { status = "okay"; }; diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi index 628a05d3f57ce..2f781258f8c99 100644 --- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi +++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_board.dtsi @@ -47,6 +47,11 @@ spi-flash@0 { }; }; +&sgpio0 { + status = "okay"; + microchip,sgpio-ports = <0x00FFFFFF>; +}; + &gpio { i2cmux_pins_i: i2cmux-pins-i { pins = "GPIO_16", "GPIO_17", "GPIO_18", "GPIO_19", -- 2.26.2
