On Mon, May 18, 2020 at 05:59:59PM +0100, Will Deacon wrote: > On Wed, May 13, 2020 at 02:33:34PM +0530, Anshuman Khandual wrote: > > Currently there are multiple instances of parange feature width mask open > > encodings while fetching it's value. Even the width mask value (0x7) itself > > is not accurate. It should be (0xf) per ID_AA64MMFR0_EL1.PARange[3:0] as in > > ARM ARM (0487F.a). Replace them with cpuid_feature_extract_unsigned_field() > > which can extract given standard feature (4 bits width i.e 0xf mask) field. > > > > Cc: Catalin Marinas <[email protected]> > > Cc: Will Deacon <[email protected]> > > Cc: Marc Zyngier <[email protected]> > > Cc: James Morse <[email protected]> > > Cc: [email protected] > > Cc: [email protected] > > Cc: [email protected] > > > > Signed-off-by: Anshuman Khandual <[email protected]> > > --- > > Changes in V2: > > > > - Used cpuid_feature_extract_unsigned_field() per Mark > > > > Changes in V1: (https://patchwork.kernel.org/patch/11541913/) > > > > arch/arm64/kernel/cpufeature.c | 3 ++- > > arch/arm64/kvm/reset.c | 11 ++++++++--- > > 2 files changed, 10 insertions(+), 4 deletions(-) > > Acked-by: Will Deacon <[email protected]> > > I'm assuming Marc will take this, but let me know if it should go via arm64 > instead (where we have a bunch of other cpufeature stuff queued).
Hmm, but having just spotted [1], it looks like we might need a bit of co-ordination here. Marc? Will [1] https://lore.kernel.org/r/[email protected]
