On Wed, May 06, 2020 at 08:42:30PM +0300, [email protected] wrote: > From: Serge Semin <[email protected]> > > When XPA mode is enabled the normally 32-bits MAAR pair registers > are extended to be of 64-bits width as in pure 64-bits MIPS > architecture. In this case the MAAR registers can enable the > speculative loads/stores for addresses of up to 39-bits width. > But in this case the process of the MAAR initialization changes a bit. > The upper 32-bits of the registers are supposed to be accessed by mean > of the dedicated instructions mfhc0/mthc0 and there is a CP0.MAAR.VH > bit which should be set together with CP0.MAAR.VL as indication > of the boundary validity. All of these peculiarities were taken into > account in this commit so the speculative loads/stores would work > when XPA mode is enabled. > > Co-developed-by: Alexey Malahov <[email protected]> > Signed-off-by: Alexey Malahov <[email protected]> > Signed-off-by: Serge Semin <[email protected]> > Cc: Thomas Bogendoerfer <[email protected]> > Cc: Paul Burton <[email protected]> > Cc: Ralf Baechle <[email protected]> > Cc: Arnd Bergmann <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: [email protected] > Cc: [email protected] > --- > arch/mips/include/asm/maar.h | 17 +++++++++++++++-- > arch/mips/include/asm/mipsregs.h | 10 ++++++++++ > arch/mips/mm/init.c | 8 +++++++- > 3 files changed, 32 insertions(+), 3 deletions(-)
applied to mips-next. Thomas. -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]
