On 05/19/2020 07:14 PM, Suzuki K Poulose wrote: > On 05/19/2020 10:40 AM, Anshuman Khandual wrote: >> Enable ETS, TWED, XNX and SPECSEI features bits in ID_AA64MMFR1 register as >> per ARM DDI 0487F.a specification. >> >> Cc: Catalin Marinas <[email protected]> >> Cc: Will Deacon <[email protected]> >> Cc: Mark Rutland <[email protected]> >> Cc: Suzuki K Poulose <[email protected]> >> Cc: [email protected] >> Cc: [email protected] >> >> Suggested-by: Will Deacon <[email protected]> >> Signed-off-by: Anshuman Khandual <[email protected]> >> --- >> arch/arm64/include/asm/sysreg.h | 4 ++++ >> arch/arm64/kernel/cpufeature.c | 4 ++++ >> 2 files changed, 8 insertions(+) >> >> diff --git a/arch/arm64/include/asm/sysreg.h >> b/arch/arm64/include/asm/sysreg.h >> index 95fdfc5e9bd0..f9dd2c5ab074 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -734,6 +734,10 @@ >> #endif >> /* id_aa64mmfr1 */ >> +#define ID_AA64MMFR1_ETS_SHIFT 36 >> +#define ID_AA64MMFR1_TWED_SHIFT 32 >> +#define ID_AA64MMFR1_XNX_SHIFT 28 >> +#define ID_AA64MMFR1_SPECSEI_SHIFT 24 >> #define ID_AA64MMFR1_PAN_SHIFT 20 >> #define ID_AA64MMFR1_LOR_SHIFT 16 >> #define ID_AA64MMFR1_HPD_SHIFT 12 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index 7ce19f97ba73..1f10ff7df705 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -299,6 +299,10 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = >> { >> }; >> static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = { >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, >> ID_AA64MMFR1_ETS_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, >> ID_AA64MMFR1_TWED_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, >> ID_AA64MMFR1_XNX_SHIFT, 4, 0), >> + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, >> ID_AA64MMFR1_SPECSEI_SHIFT, 4, 0), > > SpecSEI must be HIGHER_SAFE, like we did for MMFR4 ? Sure, will change.
