Quoting Jolly Shah (2020-03-02 13:50:41) > From: Tejas Patel <[email protected]> > > zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock, > considering best possible combination of DIV1 and DIV2. > > To find best possible values of DIV1 and DIV2, DIV1's parent rate > should be consider and not DIV2's parent rate since it would rate of > div1 clock. Consider a below topology, > > out_clk->div2_clk->div1_clk->fixed_parent > > where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock > of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk. > > Existing code divides parent rate of div2_clk's clock instead of > div1_clk's parent rate, which is wrong. > > Fix the same by considering div1's parent clock rate. > > Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation") > Signed-off-by: Tejas Patel <[email protected]> > Signed-off-by: Jolly Shah <[email protected]> > ---
Applied to clk-next
