Seeing DW APB SSI controller doesn't support setting the exactly
requested SPI bus frequency, but only a rounded frequency determined
by means of the odd-numbered half-worded reference clock divider,
it would be good tune the SPI core up and initialize the current
transfer effective_speed_hz. By doing so the core will be able to
execute the xfer-related delays with better accuracy.
Signed-off-by: Serge Semin <sergey.se...@baikalelectronics.ru>
Cc: Georgy Vlasov <georgy.vla...@baikalelectronics.ru>
Cc: Ramil Zaripov <ramil.zari...@baikalelectronics.ru>
Cc: Alexey Malahov <alexey.mala...@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbog...@alpha.franken.de>
Cc: Arnd Bergmann <a...@arndb.de>
Cc: Feng Tang <feng.t...@intel.com>
Cc: Andy Shevchenko <andriy.shevche...@linux.intel.com>
Cc: Rob Herring <robh...@kernel.org>
Cc: linux-m...@vger.kernel.org
Cc: devicet...@vger.kernel.org
---
drivers/spi/spi-dw.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 9d6904d30104..050cb2ea0812 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -352,6 +352,7 @@ static int dw_spi_transfer_one(struct spi_controller
*master,
spi_set_clk(dws, chip->clk_div);
}
+ transfer->effective_speed_hz = dws->max_freq / chip->clk_div;
dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
cr0 = dws->update_cr0(master, spi, transfer);
--
2.26.2
