Quoting Serge Semin (2020-05-26 15:20:55) > Baikal-T1 is supposed to be supplied with a high-frequency external > oscillator. But in order to create signals suitable for each IP-block > embedded into the SoC the oscillator output is primarily connected to > a set of CCU PLLs. There are five of them to create clocks for the MIPS > P5600 cores, an embedded DDR controller, SATA, Ethernet and PCIe domains. > The last three domains though named by the biggest system interfaces in > fact include nearly all of the rest SoC peripherals. Each of the PLLs is > based on True Circuits TSMC CLN28HPM IP-core with an interface wrapper > (so called safe PLL' clocks switcher) to simplify the PLL configuration > procedure. > > This driver creates the of-based hardware clocks to use them then in > the corresponding subsystems. In order to simplify the driver code we > split the functionality up into the PLLs clocks operations and hardware > clocks declaration/registration procedures. > > Even though the PLLs are based on the same IP-core, they may have some > differences. In particular, some CCU PLLs support the output clock change > without gating them (like CPU or PCIe PLLs), while the others don't, some > CCU PLLs are critical and aren't supposed to be gated. In order to cover > all of these cases the hardware clocks driver is designed with an > info-descriptor pattern. So there are special static descriptors declared > for each PLL, which is then used to create a hardware clock with proper > operations. Additionally debugfs-files are provided for each PLL' field > to make sure the implemented rate-PLLs-dividers calculation algorithm is > correct. > > Signed-off-by: Serge Semin <[email protected]> > Cc: Alexey Malahov <[email protected]> > Cc: Arnd Bergmann <[email protected]> > Cc: Rob Herring <[email protected]> > Cc: [email protected] > Cc: [email protected] > > ---
Applied to clk-next
