Hi Fenghua, > -----Original Message----- > From: Fenghua Yu <[email protected]> > Sent: Monday, June 1, 2020 6:23 PM > To: Moger, Babu <[email protected]> > Cc: [email protected]; [email protected]; [email protected]; > [email protected]; [email protected]; [email protected]; [email protected] > Subject: Re: [PATCH] x86/resctrl: Fix memory bandwidth counter width for AMD > > On Mon, Jun 01, 2020 at 06:00:29PM -0500, Babu Moger wrote: > > Memory bandwidth is calculated reading the monitoring counter > > at two intervals and calculating the delta. It is the software’s > > responsibility to read the count often enough to avoid having > > the count roll over _twice_ between reads. > > > > The current code hardcodes the bandwidth monitoring counter's width > > to 24 bits for AMD. This is due to default base counter width which > > is 24. Currently, AMD does not implement the CPUID 0xF.[ECX=1]:EAX > > to adjust the counter width. But, the AMD hardware supports much > > wider bandwidth counter with the default width of 44 bits. > > > > Kernel reads these monitoring counters every 1 second and adjusts the > > counter value for overflow. With 24 bits and scale value of 64 for AMD, > > it can only measure up to 1GB/s without overflowing. For the rates > > above 1GB/s this will fail to measure the bandwidth. > > > > Fix the issue setting the default width to 44 bits by adjusting the > > offset. > > > > AMD future products will implement the CPUID 0xF.[ECX=1]:EAX. > > > > Signed-off-by: Babu Moger <[email protected]> > > --- > > - Sending it second time. Email client had some issues first time. > > - Generated the patch on top of > > git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git (x86/cache). > > > > arch/x86/kernel/cpu/resctrl/core.c | 8 +++++++- > > arch/x86/kernel/cpu/resctrl/internal.h | 1 + > > 2 files changed, 8 insertions(+), 1 deletion(-) > > > > diff --git a/arch/x86/kernel/cpu/resctrl/core.c > b/arch/x86/kernel/cpu/resctrl/core.c > > index 12f967c6b603..6040e9ae541b 100644 > > --- a/arch/x86/kernel/cpu/resctrl/core.c > > +++ b/arch/x86/kernel/cpu/resctrl/core.c > > @@ -983,7 +983,13 @@ void resctrl_cpu_detect(struct cpuinfo_x86 *c) > > c->x86_cache_occ_scale = ebx; > > if (c->x86_vendor == X86_VENDOR_INTEL) > > c->x86_cache_mbm_width_offset = eax & 0xff; > > - else > > + else if (c->x86_vendor == X86_VENDOR_AMD) { > > + if (eax) > > + c->x86_cache_mbm_width_offset = eax & 0xff; > > When AMD implements CPUID.0x1f.1:eax, will the offset be based on 24 or 44? > Seems it makes senses to be based on 44 because default counter width is 44.
It will be based on 24 just like Intel. So, it will be 24 + offset > > > + else > > + c->x86_cache_mbm_width_offset = > > + MBM_CNTR_WIDTH_OFFSET_AMD; > > If that's the case, you don't need this "else" because the CPUID reports > offset as 0 for default width 44. > > This will match the Intel code above. > > Otherwise, the code is awkward. Yes. It is bit awkward. Other way is to add check in rdt_get_mon_l3_config. I thought this way is better. Thanks
